2.2 Electric Fields, Voltages and Energies

• The electrical force F between two charged particles with q1 and q2 units of electronic charge separated by a distance r is given by Coulomb's law: F = kc.(q1.q2)/r^2 
• Coulomb law constant: kc = 8.988 x 10^9 m per farad

Chp 2 Current Flow & Capacitance

• Current flow (I) = q.n.vd.A 
• vd is the velocity component directed along the metal bar / drift velocity
• q is the charge on electrons (-1.6 x 10-19 c)   
• n is number of electrons per unit volume
• A is area
• To describe the current flow in a cross section of area A, we define the current density:
• J = I / A = n.e.vd

1.8 Chips and Bonds

• The surface of the wafer is cut along the boundary lines between the chips. 
• Each chip is then attached to a metallized substrate (chip carrier), which is part of the final assembled component or package
• Heating is involved in the attachment (bonding of chip to substrate) since alloying or soldering processes are used and the metallized substrate must be chosen to have the same linear thermal expansion coefficient  as silicon to prevent thermal fracture
• The linear thermal expansion coefficient is defined as the rate of fractional change of length l with temperature T
• Silicon : 2.6 x 10-6 per degree Celcius (room temperature)
• The chip circuit-to-package connections are made by gold (Au) wires that are bonded to the pads (aluminum layers that are deposited during the metallization and patterning process) and to the metal lines on the package frame
• The fabrication of the package imparts mechanical stresses in the wire bond and pull tests (a 5g weight attached to the wire ) can be used to ensure good interface bonding
• Other technique: place solder balls on the aluminum pads that coated with thin films of chrome and copper-tin to provide a reliable joint. 
• The use of solder balls allow the connection to the copper leads on the chip carrier be made without wire bonds connection 

1.7 Oxidation and Doping of Silicon

• The purity of silicon is destroyed by introducing controlled amounts of electrically active impurities - called dopants
• Dopants determine current flow in semiconductor, and the introduction of electron rich dopants (donors) and electron-deficient dopants (acceptors) determine the formation of p-n junctions, which are the heart of transistors
• After the wafers have been cut from the ingot and etch polished, one of the first step in IC processing is growth of an oxide layer on the silicon
• Oxide layers can be grown in selected areas of the wafer by depositing and patterning nitride layers which act as a barrier, masking portion of the silicon from the penetration of the oxidizing species
• Dopants are introduced by ion implantation - energetic As ions penetrate the exposed portion of Si but are blocked from the silicon in areas covered by SiO2.
• Oxide and nitride layers are deposited on silicon during later stages of circuit fabrication as insulating layers between metal lines or as an insulating protective cover

1.6 Ingots and Wafers

• ICs originate with the growth of single crystals of silicon and gallium arsenide
• The crystals are grown from the melt with the melting temperatures Tm(Si)=1414 C, Tm(GaAs)=1238 C
• In Czochralski technique:
1. the melt is contained in a crucible, quartz (crystalline SiO2) for Si or graphite (carbon) for GaAs, and is kept in a molten state by RF inductive heating
2. Liquid-encapsulated Czochralski (LEC) uses a capping layer of an inert liquid (usually boron trioxide) to cover the exposed melt
3. For growth, a seed crystal is inserted into the melt and then slowly withdrawn
4. Crystal growth occurs by freezing at the interface between the solid seed and melt
5. Crystal growth proceeds by the successive additions of layers of atomic planes at the liquid-solid interface 
• After growth and surface finishing, the ingot is cut on a diamond-tipped  saw into slices or wafers 100 - 250 thick ( depending on wafer diameter)
• The wafers are evaluated for dislocation content and resistivity
• The wafers are etch polished on one surface and then place in individual slots in plastic trays for delivery to the fabrication lines

1.5 Lithography and Patterning

• In IC technology, lithography is the process of forming patterns on the surface of a semiconductor wafer
• Steps to form a pattern on a silicon wafer:
1. Silicon with a layer of silicon oxide is coated with a layer of photoresist, a light-sensitive organic film similar to the emulsion on a photographic film
2. The resist is then exposed to ultraviolet light that passes through the clear portions of a "mask", a glass plate with precise patterns of opaque material that block the light
3. In the case of positive resist, the areas of opaque material on the surface of the mask are located where SiO2 is to remain on the surface
4. After exposure to light in selected areas, the photoresist long-chain molecules have been broken (scission process) and can be removed in an organic solvent
5. The remaining photoresist after hardening is resistant to hydrofluoric acid (HF), which etches the SiO2 but does not etch the surface of silicon
6. Final Step is to remove (strip-off) the photoresist
• The geometric pattern of a mask is now transferred to the SiO2 layer 
• Other variations on lithography process: Negative resist; Electron-beam resist; X-ray lithography; Ion-beam resist
• A liftoff process is often used to define metal lines:

1. The substrate is covered with photoresist, which is then exposed in patterns so that openings are made where the metal is to remain
2. Remove unexposed resist
3. A metal film is then deposited over the surface 
4. Remove exposed resist and metal on resist
5. Metal pattern remains on Si

• Chemical etching - liquid or gas is used to remove any material not protected by a hardened resist (negative resist)
• Dry etching with ions:
• Plasma etching uses fluorine or chlorine ions to attack SiO2
• Reactive ion beam etching (RIBE) uses reactive ions
• A complete IC generally requires between 10 - 20 lithography processing steps

1.4 Interconnection and Metallization

• In IC one usually connects the various electronic devices with metal lines in order to carry current or transport the charge
• These metal lines are separated from the substrate, except in the contact area, by insulating layers of dielectric material, usually silicon dioxide
• The metal films are deposited on the substrate, patterned using lithographic techniques and etched to remove the metal except in the desired lines
• Aluminum is often used in first-level metallization
• The interconnect lines must retain their structural integrity without deformation, loss of adhesion or penetration into the silicon during the temperature cycles encountered in subsequent processing or current densities involved in actual device operation
• The interconnects should be designed to have the minimum electrical resistance so the the voltage V is minimized for a given current I, to reduce power dissipation in an interconnect
• These constraints become major issues when the next metal levels are added to provide the connections to other circuit elements.
• Poly Si - Gate; Silicide - Source/Drain Contact; Tungsten - via openings
• The proper selection of metals and silicides is a crucial issue in integrated circuits
• The metal lines and insulating layers as well as the device itself have capacitance C associated with them
• The choice of materials in the metallization is often dictated by the requirement of a low RC time constant